IIC data bus verilog code, has passed the test with modelsim.

test011\IIC.cr.mti
.......\IIC.mpf
.......\IIC_Master.v
.......\IIC_Master.v.bak
.......\IIC_Slaver.v
.......\IIC_Slaver.v.bak
.......\IIC_tp.v
.......\IIC_tp.v.bak
.......\transcript
.......\vsim.wlf
.......\work\@i@i@c_@master\verilog.asm
.......\....\..............\verilog.rw
.......\....\..............\_primary.dat
.......\....\..............\_primary.dbs
.......\....\..............\_primary.vhd
.......\....\........slaver\verilog.asm
.......\....\..............\verilog.rw
.......\....\..............\_primary.dat
.......\....\..............\_primary.dbs
.......\....\..............\_primary.vhd
.......\....\.......tp\verilog.asm
.......\....\.........\verilog.rw
.......\....\.........\_primary.dat
.......\....\.........\_primary.dbs
.......\....\.........\_primary.vhd
.......\....\sub\verilog.asm
.......\....\...\verilog.rw
.......\....\...\_primary.dat
.......\....\...\_primary.dbs
.......\....\...\_primary.vhd
.......\....\_info
.......\....\.temp\vlogc2xzh4
.......\....\.....\vlogds2te7
.......\....\.....\vlogic16c0
.......\....\.....\vlogk2wwbe
.......\....\.....\vlogn97y2n
.......\....\.....\vlogni7yzm
.......\....\.....\vlogv4f2ww
.......\....\_vmake
.......\....\@i@i@c_@master
.......\....\@i@i@c_@slaver
.......\....\@i@i@c_tp
.......\....\sub
.......\....\_temp
.......\work
test011

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