Using FPGA to generate a sinusoidal wave, simulation files with embedded logic analyzer.

singt\data_rom.cmp
.....\data_rom.vhd
.....\.b\altsyncram_d5f2.tdf
.....\..\altsyncram_f5f2.tdf
.....\..\altsyncram_l2f2.tdf
.....\..\altsyncram_lme2.tdf
.....\..\altsyncram_r131.tdf
.....\..\altsyncram_t2f2.tdf
.....\..\cmpr_7mh.tdf
.....\..\cmpr_fnh.tdf
.....\..\cmpr_gnh.tdf
.....\..\cntr_0dc.tdf
.....\..\cntr_0id.tdf
.....\..\cntr_8id.tdf
.....\..\cntr_9fd.tdf
.....\..\cntr_dha.tdf
.....\..\cntr_mbb.tdf
.....\..\cntr_mkb.tdf
.....\..\cntr_nbc.tdf
.....\..\cntr_ria.tdf
.....\..\cntr_ubb.tdf
.....\..\cntr_ulb.tdf
.....\..\cntr_v8b.tdf
.....\..\cntr_vcc.tdf
.....\..\cntr_vlb.tdf
.....\..\decode_9ie.tdf
.....\..\sin.asm.qmsg
.....\..\sin.cbx.xml
.....\..\sin.cmp.cdb
.....\..\sin.cmp.hdb
.....\..\sin.cmp.qrpt
.....\..\sin.cmp.rdb
.....\..\sin.cmp.tdb
.....\..\sin.cmp0.ddb
.....\..\sin.dbp
.....\..\sin.db_info
.....\..\sin.eco.cdb
.....\..\sin.eds_overflow
.....\..\sin.fit.qmsg
.....\..\sin.hier_info
.....\..\sin.hif
.....\..\sin.map.cdb
.....\..\sin.map.hdb
.....\..\sin.map.qmsg
.....\..\sin.pre_map.cdb
.....\..\sin.pre_map.hdb
.....\..\sin.psp
.....\..\sin.rtlv.hdb
.....\..\sin.rtlv_sg.cdb
.....\..\sin.rtlv_sg_swap.cdb
.....\..\sin.sgdiff.cdb
.....\..\sin.sgdiff.hdb
.....\..\sin.signalprobe.cdb
.....\..\sin.sim.hdb
.....\..\sin.sim.qmsg
.....\..\sin.sim.qrpt
.....\..\sin.sim.rdb
.....\..\sin.sim.vwf
.....\..\sin.sld_design_entry.sci
.....\..\sin.sld_design_entry_dsc.sci
.....\..\sin.syn_hier_info
.....\..\sin.tan.qmsg
.....\..\sld_ela_trigger_ejq.tdf
.....\romd.mif
.....\sin.asm.rpt
.....\sin.cdf
.....\sin.done
.....\sin.fit.eqn
.....\sin.fit.rpt
.....\sin.fit.summary
.....\sin.flow.rpt
.....\sin.map.eqn
.....\sin.map.rpt
.....\sin.map.summary
.....\sin.pin
.....\sin.pof
.....\sin.qpf
.....\sin.qsf
.....\sin.qws
.....\sin.sim.rpt
.....\sin.sof
.....\sin.tan.rpt
.....\sin.tan.summary
.....\sin.vhd
.....\sin.vwf
.....\stp1.stp
.....\db
singt

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