Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: 1.3V-default Download
 Description: This one for 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u to needy students as a reference
 Downloaders recently: [More information of uploader 王宇揚]
 To Search:
File list (Check if you may need any files):
 

1.3V default.v
    

CodeBus www.codebus.net