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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2014-01-09
- Size : 1kb
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- Author ：曾***
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Introduction - If you have any usage issues, please Google them yourself
To 32 magnitude optional 20 MHZ clock frequency division.After using crossover frequency as the clock signal synchronization after level 16 counter modules.Four counter output signal can be used to control the MUX timing acquisition of data channel.
Packet file list
(Preview for download)
mux.v
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