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.............\AutoConstraint_v5_emac_v1_5_example_design.sdc
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.............\emac_standard.gise
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.............\ipcore_dir
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.............\..........\create_GTP.tcl
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.............\..........\...\_cg
.............\..........\...\...\xil_11192_5.in
.............\..........\...\...\xil_11192_5.out
.............\iseconfig
.............\.........\emac_standard.projectmgr
.............\.........\v5_emac_v1_5_example_design.xreport
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.............\run_ise.tcl
.............\run_options.txt
.............\scratchproject.prs
.............\stdout.log
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.............\......\report
.............\......\......\v5_emac_v1_5_example_design_compiler_notes.txt
.............\......\......\v5_emac_v1_5_example_design_compiler_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_compiler_warnings.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_area_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_errors.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_generated_clk.rpt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_hier_area.csv
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_hier_area_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_notes.txt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_opt_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_resourceusage.rpt
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_timing_report.xml
.............\......\......\v5_emac_v1_5_example_design_fpga_mapper_warnings.txt
.............\......\......\v5_emac_v1_5_example_design_premap_errors.txt
.............\......\......\v5_emac_v1_5_example_design_premap_notes.txt
.............\......\......\v5_emac_v1_5_example_design_premap_runstatus.xml
.............\......\......\v5_emac_v1_5_example_design_premap_warnings.txt
.............\......\v5_emac_v1_5_example_design_fpga_mapper.srr
.............\......\v5_emac_v1_5_example_design_fpga_mapper.srr_Min
.............\......\v5_emac_v1_5_example_design_fpga_mapper.szr
.............\......\v5_emac_v1_5_example_design_premap.srr
.............\......\v5_emac_v1_5_example_design_premap.szr
.............\synplicity.ucf
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.............\......\cmdrec_compiler.log
.............\......\cmdrec_fpga_mapper.log
.............\......\cmdrec_premap.log
.............\......\namekey.txt
.............\......\run_option.xml
.............\......\unisim.tlg
.............\......\unisim.v
.............\......\v5_emac_v1_5_example_design.msg
.............\......\v5_emac_v1_5_example_design.plg
.............\synwork
.............\.......\v5_emac_v1_5_example_design_compiler.srs
.............\.......\v5_emac_v1_5_example_design_premap.fse
.............\.......\v5_emac_v1_5_example_design_premap.srd
.............\