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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-10-25
  • Size : 9.06mb
  • Downloaded :1次
  • Author :xuli****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
this is a program for FPGA to control AD9640, which is useful by verilog.
Packet file list
(Preview for download)


db
..\altsyncram_au14.tdf
..\altsyncram_cu14.tdf
..\altsyncram_eu14.tdf
..\altsyncram_gu14.tdf
..\altsyncram_mu14.tdf
..\altsyncram_sv01.tdf
..\alt_synch_pipe_06d.tdf
..\alt_synch_pipe_v5d.tdf
..\a_graycounter_j5c.tdf
..\a_graycounter_nn6.tdf
..\cmpr_b66.tdf
..\cmpr_ngc.tdf
..\cmpr_qgc.tdf
..\cmpr_rgc.tdf
..\cmpr_sgc.tdf
..\cntr_23j.tdf
..\cntr_dgi.tdf
..\cntr_egi.tdf
..\cntr_ggi.tdf
..\cntr_hgi.tdf
..\cntr_igi.tdf
..\cntr_jgi.tdf
..\cntr_l6j.tdf
..\dcfifo_ejf1.tdf
..\decode_dvf.tdf
..\dffpipe_uu8.tdf
..\dffpipe_vu8.tdf
..\logic_util_heursitic.dat
..\mux_usc.tdf
..\new_AD.amm.cdb
..\new_AD.asm.qmsg
..\new_AD.asm.rdb
..\new_AD.asm_labs.ddb
..\new_AD.autoh_e4eb1.map.reg_db.cdb
..\new_AD.autos_3e921.map.reg_db.cdb
..\new_AD.cbx.xml
..\new_AD.cmp.bpm
..\new_AD.cmp.cdb
..\new_AD.cmp.hdb
..\new_AD.cmp.kpt
..\new_AD.cmp.logdb
..\new_AD.cmp.rdb
..\new_AD.cmp_merge.kpt
..\new_AD.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
..\new_AD.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
..\new_AD.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
..\new_AD.db_info
..\new_AD.eda.qmsg
..\new_AD.fit.qmsg
..\new_AD.hier_info
..\new_AD.hif
..\new_AD.idb.cdb
..\new_AD.lpc.html
..\new_AD.lpc.rdb
..\new_AD.lpc.txt
..\new_AD.map.bpm
..\new_AD.map.cdb
..\new_AD.map.hdb
..\new_AD.map.kpt
..\new_AD.map.logdb
..\new_AD.map.qmsg
..\new_AD.map.rdb
..\new_AD.map_bb.cdb
..\new_AD.map_bb.hdb
..\new_AD.map_bb.logdb
..\new_AD.pre_map.cdb
..\new_AD.pre_map.hdb
..\new_AD.root_partition.map.reg_db.cdb
..\new_AD.routing.rdb
..\new_AD.rpp.qmsg
..\new_AD.rtlv.hdb
..\new_AD.rtlv_sg.cdb
..\new_AD.rtlv_sg_swap.cdb
..\new_AD.sgate.rvd
..\new_AD.sgate_sm.rvd
..\new_AD.sgdiff.cdb
..\new_AD.sgdiff.hdb
..\new_AD.sld_design_entry.sci
..\new_AD.sld_design_entry_dsc.sci
..\new_AD.smart_action.txt
..\new_AD.sta.qmsg
..\new_AD.sta.rdb
..\new_AD.sta_cmp.8_slow_1200mv_85c.tdb
..\new_AD.syn_hier_info
..\new_AD.taw.rdb
..\new_AD.tiscmp.fastest_slow_1200mv_0c.ddb
..\new_AD.tiscmp.fastest_slow_1200mv_85c.ddb
..\new_AD.tiscmp.fast_1200mv_0c.ddb
..\new_AD.tiscmp.slow_1200mv_0c.ddb
..\new_AD.tiscmp.slow_1200mv_85c.ddb
..\new_AD.tis_db_list.ddb
..\pll_altpll.v
..\prev_cmp_new_AD.qmsg
fifo.qip
fifo.v
fifo_bb.v
greybox_tmp
...........\cbx_args.txt
incremental_db
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