- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2015-11-02
- Downloads:
- 0 Times
- Uploaded by:
- 刘东辉
Description: The use of a state machine sequence detector for detecting " 1101." With btn [1] and btn [0] as input representing 1 and 0, the current digital input digital tube display in the last one, whenever entering a new number, enter the number before the left one, in turn shows recently four digital inputs, when no input digital tube does not show any numbers. After clk clock divider is available as a detector needs a clock (recommended crossover to 190Hz), whenever the detected sequence of " 1101" appears, led [0] is lit, the digital display shows " 1101" when the pipe led [0] lights btn restore the initial state when you press [2].
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Sequence Detector\bounce.vhd
.................\clk_div.vhd
.................\display.vhd
.................\main.vhd
.................\state.vhd
Sequence Detector
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