ROM_test\ROM_test\smartgen\ROM_2K\ROM_2K.gen
........\........\........\......\ROM_2K.log
........\........\........\......\ROM_2K.v
........\........\........\......\ROM_2K.shx
........\........\........\......\ROM_2K_R0C0.mem
........\........\........\......\ROM_2K.cxf
........\........\........\smartgen.aws
........\........\........\ROM_2K_work.ixf
........\........\hdl\C51_LED.HEX
........\........\...\ROMX.HEX
........\........\...\ROM_test.v
........\........\viewdraw\vf\project.lst
........\........\........\viewdraw.ini
........\........\simulation\run.do
........\........\..........\modelsim.log
........\........\..........\postsynth\_info
........\........\..........\.........\.temp\vlogmdytfa
........\........\..........\.........\.....\vloghhjese
........\........\..........\.........\_vmake
........\........\..........\.........\@r@o@m_2@k\_primary.vhd
........\........\..........\.........\..........\verilog.psm
........\........\..........\.........\..........\_primary.dbs
........\........\..........\.........\..........\_primary.dat
........\........\..........\.........\.......test\_primary.vhd
........\........\..........\.........\...........\verilog.psm
........\........\..........\.........\...........\_primary.dbs
........\........\..........\.........\...........\_primary.dat
........\........\..........\.........\testbench\_primary.vhd
........\........\..........\.........\.........\verilog.psm
........\........\..........\.........\.........\_primary.dbs
........\........\..........\.........\.........\_primary.dat
........\........\..........\vsim.wlf
........\........\..........\wave.do
........\........\..........\modelsim.ini.sav
........\........\..........\presynth\_info
........\........\..........\........\_vmake
........\........\..........\........\@r@o@m_2@k\_primary.vhd
........\........\..........\........\..........\verilog.psm
........\........\..........\........\..........\_primary.dbs
........\........\..........\........\..........\_primary.dat
........\........\..........\........\.......test\_primary.vhd
........\........\..........\........\...........\verilog.psm
........\........\..........\........\...........\_primary.dbs
........\........\..........\........\...........\_primary.dat
........\........\..........\........\testbench\_primary.vhd
........\........\..........\........\.........\verilog.psm
........\........\..........\........\.........\_primary.dbs
........\........\..........\........\.........\_primary.dat
........\........\..........\modelsim.ini
........\........\..........\ROM_2K_R0C0.mem
........\........\.ynthesis\stdout.log
........\........\.........\.yntmp\ROM_test_flink.htm
........\........\.........\......\ROM_test_srr.htm
........\........\.........\......\ROM_test_toc.htm
........\........\.........\......\sap.log
........\........\.........\......\ROM_test.plg
........\........\.........\backup\ROM_test.srr
........\........\.........\run_options.txt
........\........\.........\ROM_test.htm
........\........\.........\ROM_test.tlg
........\........\.........\ROM_test.sap
........\........\.........\ROM_test.fse
........\........\.........\ROM_test.szr
........\........\.........\ROM_test.srd
........\........\.........\ROM_test.srm
........\........\.........\ROM_test.map
........\........\.........\ROM_test.edn
........\........\.........\ROM_test.sdf
........\........\.........\ROM_test.pdc
........\........\.........\ROM_test_sdc.sdc
........\........\.........\ROM_test.so
........\........\.........\ROM_test.areasrr
........\........\.........\ROM_test.v
........\........\.........\synthesis_identify\syntmp\ROM_test_flink.htm
........\........\.........\..................\ROM_test.srs
........\........\.........\..................\ROM_test.tlg
........\........\.........\ROM_test_syn.prj
........\........\.........\ROM_test.srr
........\........\.........\ROM_test.srs
........\........\.timulus\testbench.v
........\........\designer\impl1\count4.ide_des
........\........\........\.....\F161xb8.ide_des
........\........\........\.