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fir_noRom

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-09
  • Size : 4.89mb
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  • Author :林****
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Introduction - If you have any usage issues, please Google them yourself
desgin the 16 bits FIR Filter by VHDL
Packet file list
(Preview for download)


fir_noRom\db\add_sub_j8h.tdf
.........\..\add_sub_k8h.tdf
.........\..\fir.asm.qmsg
.........\..\fir.asm_labs.ddb
.........\..\fir.cbx.xml
.........\..\fir.cmp.bpm
.........\..\fir.cmp.cdb
.........\..\fir.cmp.ecobp
.........\..\fir.cmp.hdb
.........\..\fir.cmp.kpt
.........\..\fir.cmp.logdb
.........\..\fir.cmp.rdb
.........\..\fir.cmp.tdb
.........\..\fir.cmp0.ddb
.........\..\fir.cmp2.ddb
.........\..\fir.cmp_merge.kpt
.........\..\fir.db_info
.........\..\fir.eco.cdb
.........\..\fir.eda.qmsg
.........\..\fir.fit.qmsg
.........\..\fir.hier_info
.........\..\fir.hif
.........\..\fir.lpc.html
.........\..\fir.lpc.rdb
.........\..\fir.lpc.txt
.........\..\fir.map.bpm
.........\..\fir.map.cdb
.........\..\fir.map.ecobp
.........\..\fir.map.hdb
.........\..\fir.map.kpt
.........\..\fir.map.logdb
.........\..\fir.map.qmsg
.........\..\fir.map_bb.cdb
.........\..\fir.map_bb.hdb
.........\..\fir.map_bb.logdb
.........\..\fir.pre_map.cdb
.........\..\fir.pre_map.hdb
.........\..\fir.rtlv.hdb
.........\..\fir.rtlv_sg.cdb
.........\..\fir.rtlv_sg_swap.cdb
.........\..\fir.sgdiff.cdb
.........\..\fir.sgdiff.hdb
.........\..\fir.sld_design_entry.sci
.........\..\fir.sld_design_entry_dsc.sci
.........\..\fir.syn_hier_info
.........\..\fir.tan.qmsg
.........\..\fir.tis_db_list.ddb
.........\..\mult_kt01.tdf
.........\..\mult_qt01.tdf
.........\fir.asm.rpt
.........\fir.done
.........\fir.eda.rpt
.........\fir.fit.rpt
.........\fir.fit.smsg
.........\fir.fit.summary
.........\fir.flow.rpt
.........\fir.map.rpt
.........\fir.map.summary
.........\fir.pin
.........\fir.pof
.........\fir.qpf
.........\fir.qsf
.........\fir.qws
.........\fir.sof
.........\fir.tan.rpt
.........\fir.tan.summary
.........\fir.v
.........\fir.v.bak
.........\fir_nativelink_simulation.rpt
.........\fir_top.v.bak
.........\fir_top_tb_norom.v.bak
.........\fix_mult.v
.........\incremental_db\compiled_partitions\fir.root_partition.cmp.atm
.........\..............\...................\fir.root_partition.cmp.cfm
.........\..............\...................\fir.root_partition.cmp.dfp
.........\..............\...................\fir.root_partition.cmp.hdbx
.........\..............\...................\fir.root_partition.cmp.kpt
.........\..............\...................\fir.root_partition.cmp.logdb
.........\..............\...................\fir.root_partition.cmp.rcf
.........\..............\...................\fir.root_partition.map.atm
.........\..............\...................\fir.root_partition.map.dpi
.........\..............\...................\fir.root_partition.map.hdbx
.........\..............\...................\fir.root_partition.map.kpt
.........\..............\README
.........\simulation\modelsim\data_in.txt
.........\..........\........\data_in_hex.txt
.........\..........\........\fir.m
.........\..........\........\fir.sft
.........\..........\........\fir.vo
.........\..........\........\fir_modelsim.xrf
.........\..........\........\fir_result.txt
.........\..........\........\fir_run_msim_rtl_verilog.do
.........\..........\........\fir_run_msim_rtl_verilog.do.bak
.........\..........\........\fir_top_tb_norom.v
.........\..........\........\fir_v.sdo
.........\..........\........\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\rtl_work\@_opt\vopt27ckh9
.........\..........\........\........\.....\vopt2rdqg9
.........\..........\........\........\.....\vopt3cvw8v
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