Description: In more details:
1. The master pulls SSEL down to indicate to the slave that communication is starting (SSEL is active low).
2. The master toggles the clock eight times and sends eight data bits on its MOSI line. At the same time it receives eight data bits the slave on the MISO line.
3. The master pulls SSEL up to indicate that the transfer is over.
To Search:
File list (Check if you may need any files):
verilog\spi_clgen.v
.......\spi_defines.v
.......\spi_shift.v
.......\spi_top.v
.......\timescale.v
verilog
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