Description: verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
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File list (Check if you may need any files):
Lab01\AndOr.v
.....\Intro_Top.sct
.....\Intro_Top.spj
.....\Intro_Top.v
.....\Intro_Top.vcs
.....\Lab01_Ans\AndOr.v
.....\.........\default.cfg
.....\.........\Intro_Netlist.v
.....\.........\Intro_Top.sct
.....\.........\Intro_Top.SDF
.....\.........\Intro_Top.spj
.....\.........\Intro_Top.v
.....\.........\Intro_Top.vcs
.....\.........\Intro_TopFlat.sdf
.....\.........\Intro_TopFlat.v
.....\.........\SR.v
.....\.........\TestBench.v
.....\.........\VCS_SimRun.VCD
.....\.........\XorNor.v
.....\SR.v
.....\TestBench.v
.....\XorNor.v
.....\Lab01_Ans
Lab01