clock_gyc_system\.qsys_edit\clock_gyc_custom.xml
................\..........\filters.xml
................\..........\layout.xml
................\..........\preferences.xml
................\clock_gyc_custom\synthesis\clock_gyc_custom.debuginfo
................\................\.........\clock_gyc_custom.qip
................\................\.........\clock_gyc_custom.regmap
................\................\.........\clock_gyc_custom.v
................\................\.........\submodules\altera_avalon_sc_fifo.v
................\................\.........\..........\altera_avalon_st_pipeline_base.v
................\................\.........\..........\altera_merlin_arbitrator.sv
................\................\.........\..........\altera_merlin_burst_uncompressor.sv
................\................\.........\..........\altera_merlin_master_agent.sv
................\................\.........\..........\altera_merlin_master_translator.sv
................\................\.........\..........\altera_merlin_reorder_memory.sv
................\................\.........\..........\altera_merlin_slave_agent.sv
................\................\.........\..........\altera_merlin_slave_translator.sv
................\................\.........\..........\altera_merlin_traffic_limiter.sv
................\................\.........\..........\altera_reset_controller.sdc
................\................\.........\..........\altera_reset_controller.v
................\................\.........\..........\altera_reset_synchronizer.v
................\................\.........\..........\clock_gyc_custom_button_pio.v
................\................\.........\..........\clock_gyc_custom_epcs_flash.v
................\................\.........\..........\clock_gyc_custom_epcs_flash_boot_rom.hex
................\................\.........\..........\clock_gyc_custom_hex.v
................\................\.........\..........\clock_gyc_custom_irq_mapper.sv
................\................\.........\..........\clock_gyc_custom_jtag_uart.v
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0.v
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_addr_router.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_addr_router_001.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_cmd_xbar_demux.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_cmd_xbar_demux_001.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_cmd_xbar_mux.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_cmd_xbar_mux_005.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_id_router.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_id_router_005.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_rsp_xbar_demux.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_rsp_xbar_demux_005.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_rsp_xbar_mux.sv
................\................\.........\..........\clock_gyc_custom_mm_interconnect_0_rsp_xbar_mux_001.sv
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom.ocp
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom.sdc
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom.v
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom_bht_ram.mif
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom_dc_tag_ram.mif
................\................\.........\..........\clock_gyc_custom_nios2_qsys_gyc_custom_ic_tag_ram.mif
................\.......