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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2017-02-21
- Size : 1kb
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- Author ：asd***
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Doesn t run quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.
Packet file list
(Preview for download)
117143153fast_antilog_latest.tar
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