Description: The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU internal data path, and according to the data path and the timing of the functional modules, I design the CPU controller, thus completing the design of the CPU core. Writing the module code in Verilog language and running the lighting program on DE2, I validate and test the related functions and performance.
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8051-master
8051-master\.nclaunch.dd
8051-master\asm
8051-master\asm\cast.c
8051-master\asm\counter_test.asm
8051-master\asm\DIV16U.asm
8051-master\asm\divmul.c
8051-master\asm\fib.c
8051-master\asm\gcd.c
8051-master\asm\hex
8051-master\asm\hex\cast.hex
8051-master\asm\hex\counter_test.hex
8051-master\asm\hex\div16u.hex
8051-master\asm\hex\divmul.hex
8051-master\asm\hex\fib.hex
8051-master\asm\hex\gcd.hex
8051-master\asm\hex\int2bin.hex
8051-master\asm\hex\interrupt_test.hex
8051-master\asm\hex\lcall.hex
8051-master\asm\hex\negcnt.hex
8051-master\asm\hex\r_bank.hex
8051-master\asm\hex\serial_test.hex
8051-master\asm\hex\sort.hex
8051-master\asm\hex\sqroot.hex
8051-master\asm\hex\testall.hex
8051-master\asm\hex\timer_test.hex
8051-master\asm\hex\xram.hex
8051-master\asm\hex\xram_m.ihx
8051-master\asm\in
8051-master\asm\int2bin.c
8051-master\asm\interrupt_test.asm
8051-master\asm\in\cast.in
8051-master\asm\in\counter_test.in
8051-master\asm\in\div16u.in
8051-master\asm\in\divmul.in
8051-master\asm\in\fib.in
8051-master\asm\in\gcd.in
8051-master\asm\in\int2bin.in
8051-master\asm\in\interrupt_test.in
8051-master\asm\in\lcall.in
8051-master\asm\in\negcnt.in
8051-master\asm\in\oc8051_xrom.in
8051-master\asm\in\r_bank.in
8051-master\asm\in\serial_test.in
8051-master\asm\in\sort.in
8051-master\asm\in\sqroot.in
8051-master\asm\in\testall.in
8051-master\asm\in\test_xram.in
8051-master\asm\in\timer2_test.in
8051-master\asm\in\timer_test.in
8051-master\asm\in\xram.in
8051-master\asm\in\xram_m.in
8051-master\asm\in\xrom_test.in
8051-master\asm\lcall.asm
8051-master\asm\negcnt.c
8051-master\asm\r_bank.asm
8051-master\asm\serial_test.asm
8051-master\asm\sort.c
8051-master\asm\sqroot.c
8051-master\asm\test.asm
8051-master\asm\testall.asm
8051-master\asm\testall.c
8051-master\asm\timer2_test.asm
8051-master\asm\timer_test.asm
8051-master\asm\v
8051-master\asm\vec
8051-master\asm\vec\cast.vec
8051-master\asm\vec\counter_test.vec
8051-master\asm\vec\div16u.vec
8051-master\asm\vec\divmul.vec
8051-master\asm\vec\fib.vec
8051-master\asm\vec\gcd.vec
8051-master\asm\vec\int2bin.vec
8051-master\asm\vec\interrupt_test.vec
8051-master\asm\vec\lcall.vec
8051-master\asm\vec\negcnt.vec
8051-master\asm\vec\r_bank.vec
8051-master\asm\vec\serial_test.vec
8051-master\asm\vec\sort.vec
8051-master\asm\vec\sqroot.vec
8051-master\asm\vec\testall.vec
8051-master\asm\vec\test_xram.vec
8051-master\asm\vec\timer2_test.vec
8051-master\asm\vec\timer_test.vec
8051-master\asm\vec\xram_m.vec
8051-master\asm\vec\xrom_test.vec
8051-master\asm\v\cast.v
8051-master\asm\v\counter_test.v
8051-master\asm\v\div16u.v
8051-master\asm\v\divmul.v
8051-master\asm\v\fib.v
8051-master\asm\v\gcd.v
8051-master\asm\v\int2bin.v
8051-master\asm\v\interrupt_test.v
8051-master\asm\v\lcall.v
8051-master\asm\v\negcnt.v
8051-master\asm\v\r_bank.v
8051-master\asm\v\serial_test.v
8051-master\asm\v\sort.v
8051-master\asm\v\sqroot.v
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