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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2017-10-22
- Size : 3kb
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- Author ：ribbit******
- About ： Nobody
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Introduction - If you have any usage issues, please Google them yourself
Basic function, a serial port with parity check, master clock and the baud rate is 16 times clk
Packet file list
(Preview for download)
一个简单的UART.vhd
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