CH02_MIO\DOC\main.c
........\...\MiZ702N_CORE20161215.pdf
........\...\Miz702N_fun201561215.pdf
........\...\readme.txt
........\...\ug585-Zynq-7000-TRM.pdf
........\Miz_sys\.Xil\Vivado-12352-Administrator\coregen\aximm_temp\aximm_temp.xci
........\.......\....\..........................\.......\..........\aximm_temp.xml
........\.......\....\..........................\.......\clock_temp\clock_temp.xci
........\.......\....\..........................\.......\..........\clock_temp.xml
........\.......\Miz_sys.cache\wt\project.wpc
........\.......\.............\..\synthesis.wdf
........\.......\.............\..\synthesis_details.wdf
........\.......\.............\..\webtalk_pa.xml
........\.......\........hw\Miz_sys.lpr
........\.......\........ip_user_files\bd\system\hdl\system.v
........\.......\.....................\..\......\ip\system_processing_system7_0_0\sim\system_processing_system7_0_0.v
........\.......\.....................\ipstatic\processing_system7_bfm_v2_0\hdl\processing_system7_bfm_v2_0_5_apis.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_acp.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_gp.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_hp.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_local_params.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_reg_init.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_reg_params.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_5_unused_ports.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_afi_slave.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_hp0_1.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_hp2_3.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_rd.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_rd_4.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_wr.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_arb_wr_4.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_axi_master.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_axi_slave.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_ddrc.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_fmsw_gp.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_gen_clock.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_gen_reset.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_interconnect_model.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_intr_rd_mem.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_intr_wr_mem.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_ocmc.v
........\.......\.....................\........\...........................\...\processing_system7_bfm_v2_0_ocm_mem.v
........\.......\.....................\........\...............