Search - RS232 CONTROLLER VHDL

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[VHDL-FPGA-Verilog] 07_rs232_echo

Description: Controller RS232 in VHDL
Platform: | Size: 2048 | Author: darek | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[Driver Develop] Rs232_Recv2

Description: controller RS232 for receiving serial data at different speeds
Platform: | Size: 1024 | Author: Natacho | Hits:

[Com Port] RS232_Controller

Description: This project is a RS232 Controller used to communicate two devices.
Platform: | Size: 505856 | Author: Arley | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type