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[VHDL-FPGA-Verilog] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731136 | Author: Roy Hsu | Hits:

[VHDL-FPGA-Verilog] Xilinx_sparten3E_communication_between_key_board_a

Description: 在Xilinx Spartan-3E的开发板中，实现键盘和VGA显示器的通信的源代码，与大家分享：-In the Xilinx Spartan-3E development board, the realization of the keyboard and VGA display the source code of communication to share with you:
Platform: | Size: 2048 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] pong

Description: Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
Platform: | Size: 74752 | Author: wangfeng | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[VHDL-FPGA-Verilog] 06-50

Description: PAL decoder, spartan 3 FPGA
Platform: | Size: 171008 | Author: ass | Hits:

[VHDL-FPGA-Verilog] Bin16_BCD5

Description: it is a binary16 to BCD converter .it will work on spartan 3 xilini devices.
Platform: | Size: 1024 | Author: ali | Hits:

[VHDL-FPGA-Verilog] lcd_driver_4bit

Description: it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
Platform: | Size: 3072 | Author: ali | Hits:

[Embeded-SCM Develop] RS232.VHDL

Description: RS232 Communication function in VHDL for Spartan 3E
Platform: | Size: 1024 | Author: Tony Tan | Hits:

[VHDL-FPGA-Verilog] READ

Description: 用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate
Platform: | Size: 2048 | Author: chenxing | Hits:

[Chess Poker games] plb_tft_cntlr_ref_v1_00_c

Description: 用spartan 3 实现俄罗斯方块游戏-Spartan 3 with the realization of Tetris game
Platform: | Size: 18432 | Author: 王玉 | Hits:

[VHDL-FPGA-Verilog] Spartan-3E

Description: Spartan-3E 中文介绍（包括图解、功能介绍、使用方法、锁管脚等）-Spartan-3E Starter Kit Board User Guide
Platform: | Size: 9464832 | Author: weishangqing | Hits:

[VHDL-FPGA-Verilog] vga_geometry_xps92i_s3_v01_00_03

Description: Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.-Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.
Platform: | Size: 3730432 | Author: Praveen | Hits:

[VHDL-FPGA-Verilog] eth_phy10

Description: an ethernet physique sender. it s implemented with spartan 3E starter kit
Platform: | Size: 2048 | Author: ramdane | Hits:

[VHDL-FPGA-Verilog] rafal2

Description: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Platform: | Size: 941056 | Author: nukom | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] Wiley.FPGA.Prototyping.by.VHDL.Examples.Xilinx.Sp

Description: Wiley,FPGA Prototyping by VHDL examples Spartan 3 version,Pong Chu,
Platform: | Size: 17548288 | Author: lefteris | Hits:

[VHDL-FPGA-Verilog] wtut_edif

Description: Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Platform: | Size: 20480 | Author: shad | Hits:

[VHDL-FPGA-Verilog] wtut_sc

Description: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Platform: | Size: 106496 | Author: shad | Hits:

[VHDL-FPGA-Verilog] EDK_81

Description: 视频文件 EDK_81,xilinx spartan-3-EDK_81,xilinx spartan-3
Platform: | Size: 10857472 | Author: zhouni | Hits:

[VHDL-FPGA-Verilog] 28538604-Spartan-3E-MATLAB-Interface-Documentatio

Description: Documentation VHDL communication RS-232 with the spartan 3
Platform: | Size: 313344 | Author: JT_LADINO | Hits:
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