In accordance with the requirements of high speed digital signal processing , the algorithmof radix O4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed. With butterfly u2 nit input which is designed by parallel structure and the same address calculation , four operation codes the butterfly unit needs can be provided simultaneously to have the most data parallel and improve the speed of calculation. According to the rotation parameters memory regulation , the addresses of three rotation parame2 ters of butterfly unit are the same with simple style of address generation and similar input and output memo2 ries. The operating unit adopted is implemented by three complex calculation algorithm of multiplication si2 multaneously.

基于FPGA的基_4FFT算法的硬件实现
...............................\基于FPGA的基_4FFT算法的硬件实现.pdf

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．