Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.

clk
...\automake.log
...\clk.dhp
...\clk.ise
...\clk.ise_ISE_Backup
...\clk.vhd
...\clkdiv.cmd_log
...\clkdiv.lso
...\clkdiv.ngr
...\clkdiv.prj
...\clkdiv.stx
...\clkdiv.syr
...\clkdiv_summary.html
...\clk_tb.ant
...\clk_tb.fdo
...\clk_tb.jhd
...\clk_tb.tbw
...\clk_tb.udo
...\clk_tb.vhw
...\clk_tb.xwv
...\clk_tb.xwv_bak
...\clk_tb_bencher.prj
...\pepExtractor.prj
...\results.txt
...\test_tb_bencher.prj
...\transcript
...\vsim.wlf
...\work
...\....\clk
...\....\...\behavioral.asm
...\....\...\behavioral.dat
...\....\...\_primary.dat
...\....\clkdiv
...\....\......\behavioral.asm
...\....\......\behavioral.dat
...\....\......\_primary.dat
...\....\clk_tb
...\....\......\testbench_arch.asm
...\....\......\testbench_arch.dat
...\....\......\_primary.dat
...\....\_info
...\xst
...\...\dump.xst
...\...\........\clkdiv.prj
...\...\........\..........\ngx
...\...\........\..........\...\notopt
...\...\........\..........\...\opt
...\...\work
...\...\....\hdllib.ref
...\...\....\hdpdeps.ref
...\...\....\sub00
...\...\....\.....\vhpl00.vho
...\...\....\.....\vhpl01.vho
...\_xmsgs
...\__projnav
...\.........\clk.gfl
...\.........\clkdiv.xst
...\.........\clk_flowplus.gfl
...\.........\runXst_tcl.rsp
...\.........\sumrpt_tcl.rsp
...\__projnav.log

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