The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5

component
constraint
coreconsole
designer
........\impl1
........\.....\designer.log
........\.....\simulation
........\.....\uart_test.adb
........\.....\uart_test.dtf
........\.....\.............\verify.log
........\.....\uart_test.ide_des
........\.....\uart_test.pdb
........\.....\uart_test.pdb.depends
........\.....\uart_test.tcl
........\.....\uart_test_fp
........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
........\.....\............\projectData
........\.....\............\...........\uart_test.pdb
........\.....\............\uart_test.log
........\.....\............\uart_test.pro
hdl
...\rec.v
...\send.v
...\uart_test.v
phy_synthesis
simulation
..........\modelsim.ini
..........\modelsim.ini.sav
smartgen
........\smartgen.aws
stimulus
synthesis
.........\.recordref
.........\backup
.........\......\uart_test.srr
.........\coreip
.........\run_options.txt
.........\stdout.log
.........\syntmp
.........\......\sap.log
.........\......\uart_test.msg
.........\......\uart_test.plg
.........\......\uart_test_flink.htm
.........\......\uart_test_srr.htm
.........\......\uart_test_toc.htm
.........\traplog.tlg
.........\uart_test.areasrr
.........\uart_test.edn
.........\uart_test.fse
.........\uart_test.htm
.........\uart_test.map
.........\uart_test.sap
.........\uart_test.sdf
.........\uart_test.so
.........\uart_test.srd
.........\uart_test.srm
.........\uart_test.srr
.........\uart_test.srs
.........\uart_test.tlg
.........\uart_test_sdc.sdc
.........\uart_test_syn.prj
UART.prj
viewdraw
........\sch
........\sym
........\vf
........\..\project.lst
........\viewdraw.ini
........\wir

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