Introduction - If you have any usage issues, please Google them yourself
an electronic experiments of Verilog source code. Suitable for beginners learning Verilog reference
Packet : 115157699whole_clock_code.rar.rar filelist
my_final_clock\add3.v
my_final_clock\binary_to_BCD.v
my_final_clock\clock_alarm_set.v
my_final_clock\date_screen_set.v
my_final_clock\division.v
my_final_clock\led.v
my_final_clock\modelsim.ini
my_final_clock\my_clock.v
my_final_clock\my_clock_tb.v
my_final_clock\my_division.v
my_final_clock\o_alarm.v
my_final_clock\scan.v
my_final_clock\second.v
my_final_clock\time_screen_set.v
my_final_clock\top.v
my_final_clock\transcript
my_final_clock\vsim.wlf
my_final_clock\work\_info
my_final_clock\work\top\verilog.asm
my_final_clock\work\top\_primary.dat
my_final_clock\work\top\_primary.vhd
my_final_clock\work\top
my_final_clock\work\time_screen_set\verilog.asm
my_final_clock\work\time_screen_set\_primary.dat
my_final_clock\work\time_screen_set\_primary.vhd
my_final_clock\work\time_screen_set
my_final_clock\work\second\verilog.asm
my_final_clock\work\second\_primary.dat
my_final_clock\work\second\_primary.vhd
my_final_clock\work\second
my_final_clock\work\scan\verilog.asm
my_final_clock\work\scan\_primary.dat
my_final_clock\work\scan\_primary.vhd
my_final_clock\work\scan
my_final_clock\work\o_alarm\verilog.asm
my_final_clock\work\o_alarm\_primary.dat
my_final_clock\work\o_alarm\_primary.vhd
my_final_clock\work\o_alarm
my_final_clock\work\my_division\verilog.asm
my_final_clock\work\my_division\_primary.dat
my_final_clock\work\my_division\_primary.vhd
my_final_clock\work\my_division
my_final_clock\work\my_clock_tb\verilog.asm
my_final_clock\work\my_clock_tb\_primary.dat
my_final_clock\work\my_clock_tb\_primary.vhd
my_final_clock\work\my_clock_tb
my_final_clock\work\my_clock\verilog.asm
my_final_clock\work\my_clock\_primary.dat
my_final_clock\work\my_clock\_primary.vhd
my_final_clock\work\my_clock
my_final_clock\work\led\verilog.asm
my_final_clock\work\led\_primary.dat
my_final_clock\work\led\_primary.vhd
my_final_clock\work\led
my_final_clock\work\division\verilog.asm
my_final_clock\work\division\_primary.dat
my_final_clock\work\division\_primary.vhd
my_final_clock\work\division
my_final_clock\work\date_screen_set\verilog.asm
my_final_clock\work\date_screen_set\_primary.dat
my_final_clock\work\date_screen_set\_primary.vhd
my_final_clock\work\date_screen_set
my_final_clock\work\clock_alarm_set\verilog.asm
my_final_clock\work\clock_alarm_set\_primary.dat
my_final_clock\work\clock_alarm_set\_primary.vhd
my_final_clock\work\clock_alarm_set
my_final_clock\work\binary_to_@b@c@d\verilog.asm
my_final_clock\work\binary_to_@b@c@d\_primary.dat
my_final_clock\work\binary_to_@b@c@d\_primary.vhd
my_final_clock\work\binary_to_@b@c@d
my_final_clock\work\add3\verilog.asm
my_final_clock\work\add3\_primary.dat
my_final_clock\work\add3\_primary.vhd
my_final_clock\work\add3
my_final_clock\work
my_final_clock\clock2001.rar
my_final_clock\clock_scan_block.rar
my_final_clock