Introduction - If you have any usage issues, please Google them yourself
the CPLD or FPGA to achieve a very practical frequency circuit, as long as the input frequency, on the high precision
Packet : 25811262beipin_quartii.rar filelist
bp2\bp2.asm.rpt
bp2\bp2.bsf
bp2\bp2.done
bp2\bp2.fit.eqn
bp2\bp2.fit.rpt
bp2\bp2.fit.summary
bp2\bp2.flow.rpt
bp2\bp2.map.eqn
bp2\bp2.map.rpt
bp2\bp2.map.summary
bp2\bp2.pin
bp2\bp2.qpf
bp2\bp2.qsf
bp2\bp2.qws
bp2\bp2.sim.rpt
bp2\bp2.tan.rpt
bp2\bp2.tan.summary
bp2\bp2.vhd
bp2\bp2.vwf
bp2\talkback\bp2.asm.talkback.xml
bp2\talkback\bp2.fit.talkback.xml
bp2\talkback\bp2.map.talkback.xml
bp2\talkback\bp2.sim.talkback.xml
bp2\talkback\bp2.tan.talkback.xml
bp2\talkback
bp2\db\bp2.(0).cnf.cdb
bp2\db\bp2.(0).cnf.hdb
bp2\db\bp2.asm.qmsg
bp2\db\bp2.cbx.xml
bp2\db\bp2.cmp.cdb
bp2\db\bp2.cmp.hdb
bp2\db\bp2.cmp.qrpt
bp2\db\bp2.cmp.tdb
bp2\db\bp2.dbp
bp2\db\bp2.db_info
bp2\db\bp2.eco.cdb
bp2\db\bp2.eds_overflow
bp2\db\bp2.fit.qmsg
bp2\db\bp2.hier_info
bp2\db\bp2.hif
bp2\db\bp2.map.cdb
bp2\db\bp2.map.hdb
bp2\db\bp2.map.qmsg
bp2\db\bp2.pre_map.cdb
bp2\db\bp2.pre_map.hdb
bp2\db\bp2.psp
bp2\db\bp2.rtlv.hdb
bp2\db\bp2.rtlv_sg.cdb
bp2\db\bp2.rtlv_sg_swap.cdb
bp2\db\bp2.sgdiff.cdb
bp2\db\bp2.sgdiff.hdb
bp2\db\bp2.sim.hdb
bp2\db\bp2.sim.qmsg
bp2\db\bp2.sim.qrpt
bp2\db\bp2.sim.vwf
bp2\db\bp2.sld_design_entry.sci
bp2\db\bp2.sld_design_entry_dsc.sci
bp2\db\bp2.syn_hier_info
bp2\db\bp2.tan.qmsg
bp2\db
bp2