experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

Packet : 57578887add_sub_lab2.rar filelist
lab2\adder4.vhd
lab2\addsub.vhd
lab2\addsubtest.vhd
lab2\addsub_addsubtest_vhd_tb.fdo
lab2\addsub_addsubtest_vhd_tb.udo
lab2\automake.log
lab2\fulladder.vhd
lab2\Lab 2 Adder_by.doc
lab2\lab2.dhp
lab2\lab2.npl
lab2\pepExtractor.prj
lab2\transcript
lab2\userlang.tpl
lab2\vsim.wlf
lab2\work\adder4\behavioral.asm
lab2\work\adder4\behavioral.dat
lab2\work\adder4\_primary.dat
lab2\work\adder4
lab2\work\addsub\behavioral.asm
lab2\work\addsub\behavioral.dat
lab2\work\addsub\_primary.dat
lab2\work\addsub
lab2\work\addsub_addsubtest_vhd_tb\behavior.asm
lab2\work\addsub_addsubtest_vhd_tb\behavior.dat
lab2\work\addsub_addsubtest_vhd_tb\_primary.dat
lab2\work\addsub_addsubtest_vhd_tb
lab2\work\fulladder\behavioral.asm
lab2\work\fulladder\behavioral.dat
lab2\work\fulladder\_primary.dat
lab2\work\fulladder
lab2\work\_info
lab2\work
lab2\xst\work\hdllib.ref
lab2\xst\work\hdpdeps.ref
lab2\xst\work\sub00\vhpl00.vho
lab2\xst\work\sub00
lab2\xst\work
lab2\xst
lab2\__projnav\coregen.rsp
lab2\__projnav\createTB.err
lab2\__projnav\lab2.gfl
lab2\__projnav
lab2\__projnav.log
lab2

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