BurchED B5- X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5- X300 FPGA board, B5-SRAM module, B5-CF module and B5- FPGA-CPU-IO module

Packet : 67506247system09.rar filelist
doc\SBUG_Listing.pdf
doc\SBUG_UsersGuide.pdf
doc
rtl\S2E_B5_X300_VDU\复件 (8) 新建 文本文档.txt
rtl\S2E_B5_X300_VDU\复件 (11) 新建 文本文档.txt
rtl\S2E_B5_X300_VDU\复件 新建 文本文档.txt
rtl\S2E_B5_X300_VDU\复件 (7) 新建 文本文档.txt
rtl\S2E_B5_X300_VDU\Sys09_vdu_041121.zip
rtl\S2E_B5_X300_VDU
rtl\S2_B3_VDU\复件 (9) 新建 文本文档.txt
rtl\S2_B3_VDU\复件 (10) 新建 文本文档.txt
rtl\S2_B3_VDU\readme.txt
rtl\S2_B3_VDU\Sys09_B3_VDU.zip
rtl\S2_B3_VDU
rtl\BurchED B3 Spartan2+\Sys09_VDU_Starter.zip
rtl\BurchED B3 Spartan2+
rtl\vhdl\System09_tb.vhd
rtl\vhdl\miniuart3_testbench.vhd
rtl\vhdl\noice09_rom2k_b4
rtl\vhdl\System09.npl
rtl\vhdl\attic
rtl\vhdl\System09.vhd
rtl\vhdl\复件 (6) 新建 文本文档.txt
rtl\vhdl\my_testbench1.vhd
rtl\vhdl\my_testbench2.vhd
rtl\vhdl\ps2_keyboard_interface.vhd
rtl\vhdl\block_ram.vhd
rtl\vhdl\bootrom.vhdl
rtl\vhdl\char_rom.vhd
rtl\vhdl\cpu09.vhd
rtl\vhdl\datram.vhd
rtl\vhdl\ioport.vhd
rtl\vhdl\keyboard.vhd
rtl\vhdl\miniuart.vhd
rtl\vhdl\mon_rom.vhd
rtl\vhdl\Ram2k.vhd
rtl\vhdl\rxunit3.vhd
rtl\vhdl\sbug.vhd
rtl\vhdl\sbug_rom.vhd
rtl\vhdl\system09.ucf
rtl\vhdl\timer.vhd
rtl\vhdl\Trap.vhd
rtl\vhdl\txunit2.vhd
rtl\vhdl\vdu8.vhd
rtl\vhdl
rtl

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