FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be full, etc.) of the state line.

FIFO_Buffer.v
Ser_Par_Conv_32.v
t_FIFO_Buffer.v
t_FIFO_Clock_Domain_Synch.v
t_Ser_Par_Conv_32.v
write_synch.v

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