7 segment display using verilog interfacing fpga and 7 segment display

segment
.......\segment.bgn
.......\segment.bit
.......\segment.bld
.......\segment.cmd_log
.......\segment.drc
.......\segment.ise
.......\segment.ise_ISE_Backup
.......\segment.lfp
.......\segment.lso
.......\segment.ncd
.......\segment.ngc
.......\segment.ngd
.......\segment.ngr
.......\segment.pad
.......\segment.par
.......\segment.pcf
.......\segment.prj
.......\segment.stx
.......\segment.syr
.......\segment.twr
.......\segment.twx
.......\segment.ucf
.......\segment.unroutes
.......\segment.ut
.......\segment.v
.......\segment.xpi
.......\segment.xst
.......\segment_last_par.ncd
.......\segment_map.mrp
.......\segment_map.ncd
.......\segment_map.ngm
.......\segment_pad.csv
.......\segment_pad.txt
.......\segment_summary.html
.......\segment_vhdl.prj
.......\xst
.......\...\dump.xst
.......\...\........\segment.prj
.......\...\........\...........\ngx
.......\...\........\...........\...\notopt
.......\...\........\...........\...\opt
.......\...\projnav.tmp
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\vlg1B
.......\...\....\.....\segment.bin
.......\_impact.cmd
.......\_impact.log
.......\_ngo
.......\....\netlist.lst
.......\_xmsgs
.......\......\bitgen.xmsgs
.......\......\map.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\par.xmsgs
.......\......\trce.xmsgs
.......\......\xst.xmsgs

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