This is a VGA display hardware circuit design, is written in Verilog HDL language, the supply of hardware circuit designers to use

VGA_LCD
.......\bench
.......\.....\generic_dpram.v
.......\.....\generic_spram.v
.......\.....\sync_check.v
.......\.....\tests.v
.......\.....\test_bench_top.v
.......\.....\timescale.v
.......\.....\vga_clkgen.v
.......\.....\vga_colproc.v
.......\.....\vga_csm_pb.v
.......\.....\vga_curproc.v
.......\.....\vga_cur_cregs.v
.......\.....\vga_defines.v
.......\.....\vga_enh_top.v
.......\.....\vga_fifo.v
.......\.....\vga_fifo_dc.v
.......\.....\vga_pgen.v
.......\.....\vga_tgen.v
.......\.....\vga_vtim.v
.......\.....\vga_wb_master.v
.......\.....\vga_wb_slave.v
.......\.....\wb_b3_check.v
.......\.....\wb_mast_model.v
.......\.....\wb_model_defines.v
.......\.....\wb_slv_model.v
.......\doc
.......\...\vga_core_enh.doc
.......\rtl
.......\...\generic_dpram.v
.......\...\generic_spram.v
.......\...\timescale.v
.......\...\vga_clkgen.v
.......\...\vga_colproc.v
.......\...\vga_csm_pb.v
.......\...\vga_curproc.v
.......\...\vga_cur_cregs.v
.......\...\vga_defines.v
.......\...\vga_enh_top.v
.......\...\vga_fifo.v
.......\...\vga_fifo_dc.v
.......\...\vga_pgen.v
.......\...\vga_tgen.v
.......\...\vga_vtim.v
.......\...\vga_wb_master.v
.......\...\vga_wb_slave.v
.......\sim
.......\...\bin
.......\...\...\Makefile.txt
.......\...\run
.......\software
.......\........\drviers
.......\........\include
.......\........\.......\oc_vga_lcd.h
.......\........\新建文件夹
.......\........\..........\TortoiseCVS-1.10.6.exe
.......\syn
.......\...\bin
.......\...\...\comp.dc
.......\...\...\design_spec.dc
.......\...\...\lib_spec.dc
.......\...\...\read.dc
.......\...\log
.......\...\out
.......\...\run

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