NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array. To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.

am30lv0064d.spc
AM30LV0064D_22203.pdf
amd_flash_denali.vhd
amd_flash_tb.vhd
k9f4008w0a.pdf
k9f4008w0a.soma
nand_interface.fit
nand_interface.v
pkg_convert.vhd
README.txt
samsung_flash_denali.vhd
samsung_flash_tb.vhd
time_sim.vhd
wave.do

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