A full-reducing device implementation of VHDL language, using two and a half to achieve full device functionality by

suber
.....\db
.....\..\prev_cmp_suber.asm.qmsg
.....\..\prev_cmp_suber.fit.qmsg
.....\..\prev_cmp_suber.map.qmsg
.....\..\prev_cmp_suber.qmsg
.....\..\prev_cmp_suber.sim.qmsg
.....\..\prev_cmp_suber.tan.qmsg
.....\..\suber.asm.qmsg
.....\..\suber.cbx.xml
.....\..\suber.cmp.cdb
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.....\..\suber.cmp.rdb
.....\..\suber.cmp.tdb
.....\..\suber.cmp0.ddb
.....\..\suber.db_info
.....\..\suber.eco.cdb
.....\..\suber.eds_overflow
.....\..\suber.fit.qmsg
.....\..\suber.fnsim.hdb
.....\..\suber.fnsim.qmsg
.....\..\suber.hier_info
.....\..\suber.hif
.....\..\suber.lpc.html
.....\..\suber.lpc.rdb
.....\..\suber.lpc.txt
.....\..\suber.map.cdb
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.....\..\suber.pre_map.cdb
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.....\..\suber.rtlv.hdb
.....\..\suber.rtlv_sg.cdb
.....\..\suber.rtlv_sg_swap.cdb
.....\..\suber.sgdiff.cdb
.....\..\suber.sgdiff.hdb
.....\..\suber.sim.cvwf
.....\..\suber.sim.hdb
.....\..\suber.sim.qmsg
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.....\..\suber.simfam
.....\..\suber.sld_design_entry.sci
.....\..\suber.sld_design_entry_dsc.sci
.....\..\suber.syn_hier_info
.....\..\suber.tan.qmsg
.....\..\suber.tis_db_list.ddb
.....\..\suber.tmw_info
.....\..\wed.wsf
.....\incremental_db
.....\..............\compiled_partitions
.....\..............\...................\suber.root_partition.map.kpt
.....\..............\README
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.....\suber.done
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.....\suber.tan.rpt
.....\suber.tan.summary
.....\suber.vhd
.....\suber.vhd.bak
.....\suber.vwf

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