CS valid after the first 1.5 to 2 conversion cycle, ADS7816 sampling the input signal, this time three-state output pin Dout was, DCL K after the first two falling, Dout enable and outputs a clock cycle of low invalid signal, in the next 12 DCL K cycle, Dout output conversion results, the output data format is the most significant bit (B11-bit) in the former, when the least significant bit (B0-bit) output, if the CS becomes high potential, then the end of a conversion, the maximum conversion rate of 200kHz

ads7816.c

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