This program is a counter

aula1\.lso
.....\aula1.gise
.....\aula1.ise
.....\aula1.ntrc_log
.....\aula1.xise
.....\....._xdb\cst.xbcd
.....\.........\tmp\ise\version
.....\.........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
.....\.........\...\...\............\..................\.........\HDProject_StrTbl
.....\.........\...\...\............\..................\__stored_object_table__
.....\.........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
.....\.........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
.....\.........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
.....\.........\...\...\............\................\................\dpm_project_main_StrTbl
.....\.........\...\...\............\................Gui\CViewSelector
.....\.........\...\...\............\...................\CViewSelector_StrTbl
.....\.........\...\...\............\...................\File-SynthesisOnly
.....\.........\...\...\............\...................\File-SynthesisOnly_StrTbl
.....\.........\...\...\............\...................\Library-SynthesisOnly
.....\.........\...\...\............\...................\Library-SynthesisOnly_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-_StrTbl
.....\.........\...\...\............\...................\Process-SynthesisOnly-
.....\.........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
.....\.........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
.....\.........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
.....\.........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
.....\.........\...\...\............\...................\Process-SynthesisOnly-_StrTbl
.....\.........\...\...\............\...................\Source-BehavioralSim-AutoCompile
.....\.........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
.....\.........\...\...\............\...................\Source-SynthesisOnly-AutoCompile
.....\.........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
.....\.........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
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.....\.........\...\...\............\.......\Gc_RvReportViewer-Module-Data-counter
.....\.........\...\...\............\.......\Gc_RvReportViewer-Module-Data-counter_StrTbl
.....\.........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.....\.........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
.....\.........\...\...\..REGISTRY__\Autonym\regkeys
.....\.........\...\...\............\bitgen\regkeys
.....\.........\...\...\............\...init\regkeys
.....\.........\...\...\............\common\regkeys
.....\.........\...\...\............\.pldfit\regkeys
.....\.........\...\...\............\dumpngdio\regkeys
.....\.........\...\...\............\ExpandedNetlistEngine\regkeys
.....\.........\...\...\............\fuse\regkeys
.....\.........\...\...\............\HierarchicalDesign\HDProject\regkeys
.....\.........\...\...\............\..................\regkeys
.....\.........\...\...\............\hprep6\regkeys
.....\.........\...\...\............\idem\regkeys
.....\.........\...\...\............\libgen\regkeys
.....\.........\...\...\............\map\regkeys
.....\.........\...\...\............\netgen\regkeys
.....\.........\...\...\............\.gc2edif\regkeys
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.....\.........\...\...\............\par\regkeys
.....\.........\...\...\............\.la

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