vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series

Packet : 67506278quartusii_clock.rar filelist
5_3\03281142.asm.rpt
5_3\03281142.done
5_3\03281142.fit.rpt
5_3\03281142.fit.smsg
5_3\03281142.fit.summary
5_3\03281142.flow.rpt
5_3\03281142.map.rpt
5_3\03281142.map.summary
5_3\03281142.pin
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5_3\03281142.qpf
5_3\03281142.qsf
5_3\03281142.qws
5_3\03281142.sof
5_3\03281142.tan.rpt
5_3\03281142.tan.summary
5_3\03281142.tcl
5_3\altpllpll.cmp
5_3\altpllpll.ppf
5_3\altpllpll.vhd
5_3\altpllpll_0.cmp
5_3\altpllpll_0.ppf
5_3\altpllpll_0.vhd
5_3\Chain1.cdf
5_3\cpu.ocp
5_3\cpu.vhd
5_3\cpu.vho
5_3\cpu_ic_tag_ram.mif
5_3\cpu_jtag_debug_module.vhd
5_3\cpu_jtag_debug_module_wrapper.vhd
5_3\cpu_mult_cell.vhd
5_3\cpu_ociram_default_contents.mif
5_3\cpu_rf_ram_a.mif
5_3\cpu_rf_ram_b.mif
5_3\cpu_test_bench.vhd
5_3\jtag_uart.vhd
5_3\lcd_display.vhd
5_3\led_pio.vhd
5_3\nios2.bsf
5_3\nios2.ptf
5_3\nios2.v
5_3\nios2.vhd
5_3\nios2_generation_script
5_3\nios2_log.txt
5_3\nios2_setup_quartus.tcl
5_3\pll.vhd
5_3\reconfig_request_pio.vhd
5_3\sdram.vhd
5_3\sdram_test_component.vhd
5_3\sopc_builder_debug_log.txt
5_3\sys_clk_timer.vhd
5_3\test1.bdf
5_3\.sopc_builder\install.ptf
5_3\.sopc_builder
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5_3\db\03281142.asm.qmsg
5_3\db\03281142.cbx.xml
5_3\db\03281142.cmp.cdb
5_3\db\03281142.cmp.hdb
5_3\db\03281142.cmp.kpt
5_3\db\03281142.cmp.logdb
5_3\db\03281142.cmp.rdb
5_3\db\03281142.cmp.tdb
5_3\db\03281142.cmp0.ddb
5_3\db\03281142.dbp
5_3\db\03281142.db_info
5_3\db\03281142.eco.cdb
5_3\db\03281142.fit.qmsg
5_3\db\03281142.hier_info
5_3\db\03281142.hif
5_3\db\03281142.map.cdb
5_3\db\03281142.map.hdb
5_3\db\03281142.map.logdb
5_3\db\03281142.map.qmsg
5_3\db\03281142.pre_map.cdb
5_3\db\03281142.pre_map.hdb
5_3\db\03281142.psp
5_3\db\03281142.pss
5_3\db\03281142.rtlv.hdb
5_3\db\03281142.rtlv_sg.cdb
5_3\db\03281142.rtlv_sg_swap.cdb
5_3\db\03281142.sgdiff.cdb
5_3\db\03281142.sgdiff.hdb
5_3\db\03281142.signalprobe.cdb
5_3\db\03281142.sld_design_entry.sci
5_3\db\03281142.sld_design_entry_dsc.sci
5_3\db\03281142.syn_hier_info
5_3\db\03281142.tan.qmsg
5_3\db\altsyncram_00e1.tdf
5_3\db\altsyncram_10e1.tdf
5_3\db\altsyncram_8q62.tdf
5_3\db\altsyncram_kml1.tdf
5_3\db\altsyncram_nnb1.tdf
5_3\db\altsyncram_puv1.tdf
5_3\db\altsyncram_r9e1.tdf
5_3\db\a_dpfifo_jm21.tdf
5_3\db\a_fefifo_7cf.tdf
5_3\db\cntr_bd7.tdf
5_3\db\cntr_te8.tdf
5_3\db\decode_lhi.tdf
5_3\db\dpram_ga21.tdf
5_3\db\mult_add_1f72.tdf
5_3\db\scfifo_cg21.tdf
5_3\db
5_3\nios2_sim\atail-f.pl
5_3\nios2_sim\cpu_ic_tag_ram.dat
5_3\nios2_sim\cpu_ic_tag_ram.hex
5_3\nios2_sim\cpu_ociram_default_contents.dat
5_3\nios2_sim\cpu_ociram_default_contents.hex
5_3\nios2_sim\cpu_rf_ram_a.dat
5_3\nios2_sim\cpu_rf_ram_a.hex
5_3\nios2_sim\cpu_rf_ram_b.dat
5_3\nios2_sim\cpu_rf_ram_b.hex
5_3\nios2_sim\create_nios2_project.do
5_3\nios2_sim\ext_flash.dat
5_3\nios2_sim\ext_flash.sym
5_3\nios2_sim\ext_ram.dat
5_3\nios2_sim\ext_ram.sym
5_3\nios2_sim\ext_ram_lane0.dat
5_3\nios2_sim\ext_ram_lane1.dat
5_3\nios2_sim\ext_ram_lane2.dat
5_3\nios2_sim\ext_ram_lane3.dat
5_3\nios2_sim\jtag_uart_input_mutex.dat
5_3\nios2_sim\jtag_uart_input_stream.dat
5_3\nios2_sim\jtag_uart_log.bat
5_3\nios2_sim\jtag_uart_output_stream.dat
5_3\nios2_sim\list_presets.do
5_3\nios2_sim\modelsim.tcl
5_3\nios2_sim\sdram.dat
5_3\nios2_sim\sdram.sym
5_3\nios2_sim\setup_sim.do
5_3\nios2_sim\virtuals.do
5_3\nios2_sim\wave_presets.do
5_3\nios2_sim
5_3\software\traffic.h
5_3\software\traffic_light.c
5_3\software\.metadata\.lock
5_3\software\.metadata\.log
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5_3

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