Write Verilog FPGA-based phase detector module

Verilog编写基于FPGA的鉴相器模块\PD_using_FPGA\phase_control.bdf
...............................\.............\......test\db\add_sub_nsh.tdf
...............................\.............\..........\..\cntr_2ii.tdf
...............................\.............\..........\..\phase_test.asm.qmsg
...............................\.............\..........\..\phase_test.cbx.xml
...............................\.............\..........\..\phase_test.cmp.cdb
...............................\.............\..........\..\phase_test.cmp.hdb
...............................\.............\..........\..\phase_test.cmp.kpt
...............................\.............\..........\..\phase_test.cmp.logdb
...............................\.............\..........\..\phase_test.cmp.rdb
...............................\.............\..........\..\phase_test.cmp.tdb
...............................\.............\..........\..\phase_test.cmp0.ddb
...............................\.............\..........\..\phase_test.dbp
...............................\.............\..........\..\phase_test.db_info
...............................\.............\..........\..\phase_test.eco.cdb
...............................\.............\..........\..\phase_test.eds_overflow
...............................\.............\..........\..\phase_test.fit.qmsg
...............................\.............\..........\..\phase_test.fnsim.hdb
...............................\.............\..........\..\phase_test.fnsim.qmsg
...............................\.............\..........\..\phase_test.hier_info
...............................\.............\..........\..\phase_test.hif
...............................\.............\..........\..\phase_test.map.cdb
...............................\.............\..........\..\phase_test.map.hdb
...............................\.............\..........\..\phase_test.map.logdb
...............................\.............\..........\..\phase_test.map.qmsg
...............................\.............\..........\..\phase_test.pre_map.cdb
...............................\.............\..........\..\phase_test.pre_map.hdb
...............................\.............\..........\..\phase_test.psp
...............................\.............\..........\..\phase_test.rtlv.hdb
...............................\.............\..........\..\phase_test.rtlv_sg.cdb
...............................\.............\..........\..\phase_test.rtlv_sg_swap.cdb
...............................\.............\..........\..\phase_test.sgdiff.cdb
...............................\.............\..........\..\phase_test.sgdiff.hdb
...............................\.............\..........\..\phase_test.signalprobe.cdb
...............................\.............\..........\..\phase_test.sim.hdb
...............................\.............\..........\..\phase_test.sim.qmsg
...............................\.............\..........\..\phase_test.sim.rdb
...............................\.............\..........\..\phase_test.sim.vwf
...............................\.............\..........\..\phase_test.sld_design_entry.sci
...............................\.............\..........\..\phase_test.sld_design_entry_dsc.sci
...............................\.............\..........\..\phase_test.smp_dump.txt
...............................\.............\..........\..\phase_test.syn_hier_info
...............................\.............\..........\..\phase_test.tan.qmsg
...............................\.............\..........\..\wed.zsf
...............................\.............\..........\phase_counter.bsf
...............................\.............\..........\phase_counter.inc
...............................\.............\..........\phase_counter.v
...............................\.............\..........\phase_counter_bb.v
...............................\.............\..........\phase_pll.bsf
...............................\.............\..........\phase_pll.inc
...............................\.............\..........\phase_pll.ppf
...............................\.............\..........

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