Code for VHDL authomatic generation since High Level tools as CatapultC

canceladorDSP_singleport\catapult.log
........................\Catapult_C\SIF\project.sif
........................\..........\...\sid1__compile.sif
........................\..........\...\sid2__allocation.sif
........................\..........\...\sid2__compile.sif
........................\..........\...\sid2__dpfsm.sif
........................\..........\...\sid2__extracted.sif
........................\..........\...\sid2__hardware.sif
........................\..........\...\sid2__interface.sif
........................\..........\...\sid2__loops.sif
........................\..........\...\sid2__memories.sif
........................\..........\...\sid2__scheduling.sif
........................\..........\...\sid3__allocation.sif
........................\..........\...\sid3__compile.sif
........................\..........\...\sid3__dpfsm.sif
........................\..........\...\sid3__extracted.sif
........................\..........\...\sid3__hardware.sif
........................\..........\...\sid3__interface.sif
........................\..........\...\sid3__loops.sif
........................\..........\...\sid3__memories.sif
........................\..........\...\sid3__scheduling.sif
........................\..........\.olution_2\.cycle.rpt.xrf
........................\..........\..........\.cycle.vhdl.xrf
........................\..........\..........\.rtl.rpt.xrf
........................\..........\..........\.rtl.vhdl.xrf
........................\..........\..........\critical.nlv
........................\..........\..........\cycle.rpt
........................\..........\..........\cycle.vhdl
........................\..........\..........\cycle.vhdl.msim
........................\..........\..........\datapath.nlv
........................\..........\..........\mgc_hls\funcs\body.asm
........................\..........\..........\.......\.....\body.dat
........................\..........\..........\.......\.....\_primary.dat
........................\..........\..........\.......\.....\_vhdl.asm
........................\..........\..........\.......\mgc_comps\_primary.dat
........................\..........\..........\.......\.........\_vhdl.asm
........................\..........\..........\.......\....shift_l\beh.asm
........................\..........\..........\.......\...........\beh.dat
........................\..........\..........\.......\...........\_primary.dat
........................\..........\..........\.......\..........r\beh.asm
........................\..........\..........\.......\...........\beh.dat
........................\..........\..........\.......\...........\_primary.dat
........................\..........\..........\.......\_info
........................\..........\..........\rtl.nlv
........................\..........\..........\rtl.rpt
........................\..........\..........\rtl.vhdl
........................\..........\..........\rtl.vhdl.msim
........................\..........\..........\rtl.vhdl.psr
........................\..........\..........\siflibs\mgc_inout_buf_wait\beh.asm
........................\..........\..........\.......\..................\beh.dat
........................\..........\..........\.......\..................\_primary.dat
........................\..........\..........\.......\..........fifo_wait\beh.asm
........................\..........\..........\.......\...................\beh.dat
........................\..........\..........\.......\...................\_primary.dat
........................\..........\..........\.......\..........stdreg_en\beh.asm
........................\..........\..........\.......\...................\beh.dat
........................\..........\..........\.......\...................\_primary.dat
........................\..........\..........\.......\.................wait\beh.asm
........................\..........\..........\.......\.....................\beh.dat
........................\..........\..........\.......\.....................\_primary.dat
........................\..........\..........\.......\......_wire\beh.asm
....

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