Xilinx DSP Design with Matlab binding assay.

XDSP
....\lab4
....\....\aspec_cspec1.m
....\....\bandpass_filter.bak
....\....\bandpass_filter.mdl
....\....\coef.m
....\....\interpolatedFIR.fda
....\....\interpolatedFIR.mdl
....\....\interpolatedfir_interpolated_fir.mrp
....\....\interpolatedfir_normal_fir.mrp
....\....\lab4_soln
....\....\.........\aspec_cspec1.m
....\....\.........\bandpass_filter.mdl
....\....\.........\bandpass_filter_config.m
....\....\.........\bandpass_filter_hwcosim.mdl
....\....\.........\bandpass_filter_hwcosim_config.m
....\....\.........\bandpass_filter_hwcosim_hwcosim_lib.mdl
....\....\.........\board
....\....\.........\.....\automake.log
....\....\.........\.....\bandpass_filter_hwcosim.vhd
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper.bit
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper.dhp
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper.npl
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper.vhd
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper.xcf
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper_config.cmd
....\....\.........\.....\bandpass_filter_hwcosim_clk_wrapper_config.log
....\....\.........\.....\bandpass_filter_hwcosim_clock_driver.vhd
....\....\.........\.....\bandpass_filter_hwcosim_config.m
....\....\.........\.....\bandpass_filter_hwcosim_dcm_wrapper.vhd
....\....\.........\.....\bandpass_filter_hwcosim_FIR.coe
....\....\.........\.....\bandpass_filter_hwcosim_FIR.mif
....\....\.........\.....\bandpass_filter_hwcosim_fir.vhd
....\....\.........\.....\bandpass_filter_hwcosim_hwcosim_lib.mdl
....\....\.........\.....\clkwrapperinterface
....\....\.........\.....\clkwrapperinterface.txt
....\....\.........\.....\clock_pkg.vhd
....\....\.........\.....\conv_pkg.vhd
....\....\.........\.....\coregen_tmp
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.mif
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.v
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.veo
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.xco
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.xcp
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e_flist.txt
....\....\.........\.....\dcmwrapperinterface
....\....\.........\.....\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
....\....\.........\.....\globals
....\....\.........\.....\jtagcosim_top.ucf
....\....\.........\.....\jtagcosim_top.vhd
....\....\.........\.....\postnetlist.log
....\....\.........\.....\sync_fifo.vhd
....\....\.........\.....\synth_model
....\....\.........\.....\...........\bandpass_filter_hwcosim.vhd
....\....\.........\.....\...........\bandpass_filter_hwcosim_clk_wrapper.lso
....\....\.........\.....\...........\bandpass_filter_hwcosim_clk_wrapper.ngc
....\....\.........\.....\...........\bandpass_filter_hwcosim_clk_wrapper.results
....\....\.........\.....\...........\bandpass_filter_hwcosim_clk_wrapper.vhd
....\....\.........\.....\...........\bandpass_filter_hwcosim_clk_wrapper.xcf
....\....\.........\.....\...........\bandpass_filter_hwcosim_clock_driver.vhd
....\....\.........\.....\...........\bandpass_filter_hwcosim_fir.vhd
....\....\.........\.....\...........\clock_pkg.vhd
....\....\.........\.....\...........\commandLines
....\....\.........\.....\...........\conv_pkg.vhd
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.edn
....\....\.........\.....\...........\distributed_arithmetic_fir_filter_spartan2_8_0_b0cf4f8b28bc6b9e.ngo
....\....\.........\.....\...........\sync_fifo.vhd
....\....\.........\.....\...........\synth_reg.vhd
....\....\.........\.....\...........\synth_reg_w_init.vhd
....\....\.........\....

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