The system consists of two DSP components, complete the data acquisition front-end DSP

pipeline（左端DSP）\arithmetic1.c
...................\boot\boot.dat
...................\boot.asm
...................\bootmap
...................\cc_build_Debug.log
...................\Debug\arithmetic1.obj
...................\.....\boot.obj
...................\.....\edma_cfg.obj
...................\.....\edma_cfg_1.obj
...................\.....\emif_cfg.obj
...................\.....\interrupt.obj
...................\.....\MAIN.obj
...................\.....\pipeline.out
...................\.....\timer_cfg.obj
...................\.....\vectors.obj
...................\Debug.lkf
...................\Debug.lkv
...................\edma.h
...................\edma_cfg.c
...................\emif.h
...................\emif_cfg.c
...................\interrupt.c
...................\lnkd.cmd
...................\MAIN.C
...................\para.h
...................\pipeline.paf
...................\pipeline.pjt
...................\refer_sig4.h
...................\timer_cfg.c
...................\twiddle.h
...................\vectors.asm
...................\boot
...................\Debug
pipeline（左端DSP）

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