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  • Category : USB develop
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  • Update : 2012-11-26
  • Size : 193kb
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  • Author :李****
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Introduction - If you have any usage issues, please Google them yourself
USB low-level implementation of communication code, vc ++ implementation, very practical, learning to communicate good helper. - USB communication code
Packet file list
(Preview for download)
usb_funct\bench\CVS\Root
.........\.....\...\Repository
.........\.....\...\Entries
.........\.....\CVS
.........\.....\verilog\CVS\Root
.........\.....\.......\...\Repository
.........\.....\.......\...\Entries
.........\.....\.......\CVS
.........\.....\verilog
.........\bench
.........\doc\CVS\Root
.........\...\...\Repository
.........\...\...\Entries
.........\...\CVS
.........\...\README.txt
.........\...\STATUS.txt
.........\...\usb_doc.pdf
.........\doc
.........\rtl\CVS\Root
.........\...\...\Repository
.........\...\...\Entries
.........\...\CVS
.........\...\verilog\CVS\Root
.........\...\.......\...\Repository
.........\...\.......\...\Entries
.........\...\.......\CVS
.........\...\.......\usbf_crc16.v
.........\...\.......\usbf_crc5.v
.........\...\.......\usbf_defines.v
.........\...\.......\usbf_ep_rf.v
.........\...\.......\usbf_ep_rf_dummy.v
.........\...\.......\usbf_idma.v
.........\...\.......\usbf_mem_arb.v
.........\...\.......\usbf_pa.v
.........\...\.......\usbf_pd.v
.........\...\.......\usbf_pe.v
.........\...\.......\usbf_pl.v
.........\...\.......\usbf_rf.v
.........\...\.......\usbf_top.v
.........\...\.......\usbf_utmi_if.v
.........\...\.......\usbf_utmi_ls.v
.........\...\.......\usbf_wb.v
.........\...\verilog
.........\rtl
.........\sim\CVS\Root
.........\...\...\Repository
.........\...\...\Entries
.........\...\CVS
.........\...\rtl_sim\CVS\Root
.........\...\.......\...\Repository
.........\...\.......\...\Entries
.........\...\.......\CVS
.........\...\.......\bin\CVS\Root
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Entries
.........\...\.......\...\CVS
.........\...\.......\bin
.........\...\.......\run\CVS\Root
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Entries
.........\...\.......\...\CVS
.........\...\.......\run
.........\...\rtl_sim
.........\sim
.........\.yn\CVS\Root
.........\...\...\Repository
.........\...\...\Entries
.........\...\CVS
.........\...\bin\CVS\Root
.........\...\...\...\Repository
.........\...\...\...\Entries
.........\...\...\CVS
.........\...\...\comp.dc
.........\...\...\design_spec.dc
.........\...\...\lib_spec.dc
.........\...\...\read.dc
.........\...\bin
.........\...\log\CVS\Root
.........\...\...\...\Repository
.........\...\...\...\Entries
.........\...\...\CVS
.........\...\log
.........\...\out\CVS\Root
.........\...\...\...\Repository
.........\...\...\...\Entries
.........\...\...\CVS
.........\...\out
.........\...\run\CVS\Root
.........\...\...\...\Repository
.........\...\...\...\Entries
.........\...\...\CVS
.........\...\run
.........\syn
usb_funct
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