dsp, fpga, power, audio equalizer and so on. For reference use.

第二阶段\DSP\DSP子板\AD_DA_Sport.SchDoc
........\...\.......\Connector.SchDoc
........\...\.......\DSPFPGA.Dat
........\...\.......\DSPFPGA.IntLib
........\...\.......\DSPFPGA.PCB3D
........\...\.......\DSPFPGA.PcbDoc
........\...\.......\DSPFPGA.PcbDoc.htm
........\...\.......\DSPFPGA.PCBLIB
........\...\.......\DSPFPGA.pdf
........\...\.......\DSPFPGA.PRJPCB
........\...\.......\DSPFPGA.PRJPCBStructure
........\...\.......\DSPFPGA.SCHLIB
........\...\.......\DSPFPGA覆铜.PcbDocPreview
........\...\.......\History\DSPFPGA.~(1).PRJPCB.Zip
........\...\.......\Main.SchDoc
........\...\.......\Power.SchDoc
........\...\.......\Processor_BUS.SchDoc
........\...\.......\...ject Outputs for DSPFPGA\DSPFPGA.REP
........\...\.......\...........................\DSPFPGA.xls
........\...\.......\...........................\Status Report.Txt
........\...\.......\.......Outputs\Design Rule Check - DSPFPGA.drc
........\...\.......\..............\Design Rule Check - DSPFPGA.html
........\...\.......\..............\Design Rule Check - DSPFPGA覆铜.drc
........\...\.......\..............\Design Rule Check - DSPFPGA覆铜.html
........\...\.......\..............\DSPFPGA.xls
........\...\.......\Reset_Clock.SchDoc
........\...\处理器子板设计文档.doc
........\...\母板设计\DSP母板.PCBLIB
........\...\........\DSP母板.SchDoc
........\...\........\ProjectOutputs\Design Rule Check - DSP母板.drc
........\...\........\..............\Design Rule Check - DSP母板.html
........\...\........\..............\Design Rule Check - 母板PCB2.drc
........\...\........\..............\Design Rule Check - 母板PCB2.html
........\...\........\SYSTEM.PcbLib
........\...\........\母板.PRJPCB
........\...\........\母板.PRJPCB And 母板.XLS
........\...\........\母板.PRJPCB And 母板net.XLS
........\...\........\母板.PRJPCBStructure
........\...\........\母板.SCHLIB
........\...\........\母板PCB2.PCB3D
........\...\........\母板PCB2.PcbDoc
........\...\........\母板PCB2.PcbDoc.htm
........\...\........\母板PCB2.PcbLib
........\...\系统母板设计文档.doc
........\FPGA\FPGA各模块解决方案--复制.doc
........\....\....板原理图\AD.SchDoc
........\....\............\AD.SchDocPreview
........\....\............\CLOCK.SchDoc
........\....\............\Connect_to_CPU.SchDoc
........\....\............\Connect_to_CPU.SchDocPreview
........\....\............\DA.SchDoc
........\....\............\DA.SchDocPreview
........\....\............\DDS.SchDoc
........\....\............\DDS.SchDocPreview
........\....\............\FPGA PCB ECO 2009-7-17 19-51-54.LOG
........\....\............\FPGA PCB ECO 2009-7-17 20-01-06.LOG
........\....\............\FPGA PCB ECO 2009-7-17 20-06-42.LOG
........\....\............\FPGA PCB ECO 2009-7-17 20-07-25.LOG
........\....\............\fpga(new).PcbDocPreview
........\....\............\FPGA.Dat
........\....\............\fpga.IntLib
........\....\............\FPGA.OutJob
........\....\............\FPGA.PcbDoc
........\....\............\FPGA.PcbDoc.htm
........\....\............\FPGA.PcbDocPreview
........\....\............\FPGA.PRJPCB
........\....\............\FPGA.PRJPCB And FPGA.XLS
........\....\............\FPGA.PrjPcbStructure
........\....\............\FPGA.SchDoc
........\....\............\FPGA.SchDocPreview
........\....\............\....1\FPGA.LIBPKG
........\....\............\.....\fpga.PcbLib
........\....\............\.....\FPGA.SCHLIB
........\....\............\.....\fpga1.PcbLib
........\....\............\.....\History\FPGA.~(1).SCHLIB.Zip
........\....\............\.....\.......\FPGA.~(2).SCHLIB.Zip
........\....\............\FPGA1 PCB ECO 2009-7-18 22-17-27.LOG
........\....\............\FPGA1 PCB ECO 2009-7-18 22-17-52.LOG
........\....\............\FPGA1 PCB ECO 2009-7-18 22-23-21.LOG
........\....\............\FPGA1 PCB ECO 2009-7-18 22-25-34.LOG
........\....\............\FPGA1 PCB ECO 2009-7-19 10-10-08.LOG
........\....\............\FPGA1 PCB ECO 2009-7-19 10-11-48.LOG
........\....\............\FPGA1 PCB ECO 2009-7-19 16-33-19.LOG
........\....\............\FPGA1 PCB ECO 2009-7-19 16-53-37.LOG
........\....\............\FPGA1 PCB ECO 2

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