MSP-FET430P140 Demo- Timer_A, PWM TA1-2, Up Mode, DCO SMCLK // // Description: This program generates two PWM outputs on P1.2,3 using // Timer_A configured for up mode. The value in CCR0, 512-1, defines the PWM // period and the values in CCR1 and CCR2 the PWM duty cycles. Using ~800kHz // SMCLK as TACLK, the timer period is ~640us with a 75 duty cycle on P1.2 // and 25 on P1.3.

TA_13.c

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