ｍｕｔｉｌ－ｆｕｎｃｔｉｏｎ　ｄｉｇｉｔａｌ　ｃｌｏｃｋ　Verilog ＨＤＬ

多功能数字钟\clock.asm.rpt
............\clock.done
............\clock.dpf
............\clock.fit.rpt
............\clock.fit.smsg
............\clock.fit.summary
............\clock.flow.rpt
............\clock.map.rpt
............\clock.map.summary
............\clock.pin
............\clock.pof
............\clock.qpf
............\clock.qsf
............\clock.qws
............\clock.sof
............\clock.tan.rpt
............\clock.tan.summary
............\clock.v
............\clock_assignment_defaults.qdf
............\db\clock.asm.qmsg
............\..\clock.asm_labs.ddb
............\..\clock.cbx.xml
............\..\clock.cmp.cdb
............\..\clock.cmp.hdb
............\..\clock.cmp.kpt
............\..\clock.cmp.logdb
............\..\clock.cmp.rdb
............\..\clock.cmp.tdb
............\..\clock.cmp0.ddb
............\..\clock.cmp2.ddb
............\..\clock.db_info
............\..\clock.eco.cdb
............\..\clock.fit.qmsg
............\..\clock.hier_info
............\..\clock.hif
............\..\clock.lpc.html
............\..\clock.lpc.rdb
............\..\clock.lpc.txt
............\..\clock.map.cdb
............\..\clock.map.hdb
............\..\clock.map.logdb
............\..\clock.map.qmsg
............\..\clock.pre_map.cdb
............\..\clock.pre_map.hdb
............\..\clock.rtlv.hdb
............\..\clock.rtlv_sg.cdb
............\..\clock.rtlv_sg_swap.cdb
............\..\clock.sgdiff.cdb
............\..\clock.sgdiff.hdb
............\..\clock.sld_design_entry.sci
............\..\clock.sld_design_entry_dsc.sci
............\..\clock.syn_hier_info
............\..\clock.tan.qmsg
............\..\clock.tis_db_list.ddb
............\..\clock.tmw_info
............\..\clock_global_asgn_op.abo
............\incremental_db\compiled_partitions\clock.root_partition.map.kpt
............\..............\README
............\..............\compiled_partitions
............\db
............\incremental_db
多功能数字钟

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