VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u

phase_test\top.xpi
..........\top_pad.csv
..........\BCD_CODE.prj
..........\BCD_CODE.stx
..........\BCD_CODE.vhd
..........\BCD_CODE.xst
..........\phase_test.xise
..........\control.vhd
..........\controller.prj
..........\controller.stx
..........\controller.vhd
..........\controller.xst
..........\controller_vhdl.prj
..........\Counter_4096.prj
..........\Counter_4096.stx
..........\Counter_4096.vhd
..........\Counter_4096.xst
..........\Counter_4096_vhdl.prj
..........\device_usage_statistics.html
..........\display.prj
..........\display.stx
..........\display.vhd
..........\display.xst
..........\top.pad
..........\top_pad.txt
..........\top.ncd
..........\jianxiang.prj
..........\jianxiang.stx
..........\jianxiang.vhd
..........\jianxiang.xst
..........\jianxiang_vhdl.prj
..........\ll.ise_ISE_Backup
..........\ll.ntrc_log
..........\M_k_counter.prj
..........\M_k_counter.stx
..........\M_k_counter.vhd
..........\M_k_counter.xst
..........\top.unroutes
..........\BCD_CODE.spl
..........\pepExtractor.prj
..........\M_k_counter.spl
..........\phase_test.ise_ISE_Backup
..........\phase_test.ntrc_log
..........\top.bgn
..........\top.bit
..........\BCD_CODE.sym
..........\top.cmd_log
..........\top.drc
..........\top.lso
..........\__ISE_repository_phase_test.ise_.lock
..........\jianxiang.spl
..........\top.pcf
..........\top.prj
..........\top.spl
..........\top.stx
..........\top.sym
..........\top.syr
..........\top.twr
..........\top.twx
..........\top.ucf
..........\jianxiang.sym
..........\top.ut
..........\top.vhd
..........\display.spl
..........\top.xst
..........\top_fpe.prj
..........\top_guide.ncd
..........\M_k_counter.sym
..........\Counter_4096.spl
..........\top_prev_built.ngd
..........\top_summary.html
..........\Counter_4096.sym
..........\controller.spl
..........\__ISE_repository_ll.ise_.lock
..........\controller.sym
..........\display.sym
..........\_xmsgs\bitgen.xmsgs
..........\......\fuse.xmsgs
..........\......\vhpcomp.xmsgs
..........\......\pn_parser.xmsgs
..........\......\xst.xmsgs
..........\......\ngdbuild.xmsgs
..........\......\map.xmsgs
..........\......\par.xmsgs
..........\......\trce.xmsgs
..........\.ngo\netlist.lst
..........\top.vf
..........\top.sch
..........\top.jhd
..........\MK.vhd
..........\top_vhdl.prj
..........\top.ngr
..........\top.bld
..........\top.ngc
..........\top.ngd
..........\top_map.mrp
..........\top_map.map
..........\top_map.ngm
..........\top_map.ncd
..........\top_usage.xml

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