VHDL design example, the achievement of commonly used methods of logic design.

Packet : 1985492source_vhdl.zip filelist
delay.vhd
mux_8x1.vhd
or4x32_reg.vhd
output_pipeline.vhd
rd_cntrl.vhd
reg32.vhd
s2p8x32.vhd
ser_par_lib.vhd
sync.vhd
top_vhd.vhd
wr_cntrl.vhd

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