This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns

AES based on FPGA-jiami\aes_cipher_top.v
.......................\aes_cipher_top.v.bak
.......................\aes_cipher_top.vwf
.......................\aes_key_expand_128.v
.......................\aes_key_expand_128.v.bak
.......................\aes_key_expand_128.vwf
.......................\aes_sbox.v
.......................\aes_sbox.v.bak
.......................\db\logic_util_heursitic.dat
.......................\..\mux_src.tdf
.......................\..\wed.wsf
.......................\incremental_db\README
.......................\..............\compiled_partitions
.......................\db
.......................\incremental_db
AES based on FPGA-jiami

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