Introduction - If you have any usage issues, please Google them yourself
Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64.