Parallel to 5 pair HDSDI encode/decode

README.txt
DualLink\Constraints
........\...........\alp_top_dual.ucf
........\Docs
........\....\Firmware_Description_DualLink.pdf
........\....\ipt_reg_dual.txt
........\....\ipt_reg_dual.xls
........\....\RLE Dual Link 100 Bars.xls
........\....\RLE Pattern Gen Sheet.xls
........\ISE_Project
........\...........\alp_prj_dual_Verilog.ise
........\...........\alp_prj_dual_vhdl.ise
........\...........\alp_top_dual_verilog.bit
........\...........\alp_top_dual_Verilog.lso
........\...........\alp_top_dual_Verilog.prj
........\...........\alp_top_dual_Verilog.xst
........\...........\alp_top_dual_vhdl.bit
........\...........\alp_top_dual_VHDL.lso
........\...........\alp_top_dual_VHDL.prj
........\...........\alp_top_dual_VHDL.xst
........\...........\Makefile
........\...........\makefile_hdl
........\...........\okBTPipeIn.ngc
........\...........\okBTPipeOut.ngc
........\...........\okHostInterfaceCore.ngc
........\...........\okPipeIn.ngc
........\...........\okPipeOut.ngc
........\...........\okTriggerIn.ngc
........\...........\okTriggerOut.ngc
........\...........\okWireIn.ngc
........\...........\okWireOut.ngc
........\RTL_Common
........\..........\alpIfDecode_fa01.v
........\..........\alpIfHandler_fa01.v
........\..........\alpPortReg_fa01.v
........\..........\alpReg_fa02.v
........\..........\ClkChkGen_fa01.v
........\..........\EZLinkALP_h_fa02.v
........\..........\i2c_master_bit_ctrl.v
........\..........\i2c_master_byte_ctrl.v
........\..........\i2c_master_defines.v
........\..........\i2c_master_top.v
........\..........\meta_fa01.v
........\..........\okLibrary.v
........\..........\ok_h_fa01.v
........\..........\qi2c_fa01.v
........\..........\qi2c_h_fa01.v
........\..........\qi2c_sm_fa01.v
........\..........\qi2c_wrapper_fa01.v
........\..........\qsmb_h_fa01.v
........\..........\qsmb_sm_fa01.v
........\..........\smbus_fa01.v
........\..........\ubusDecode_fa02.v
........\..........\ubus_sm_fa01.v
........\RTL_Verilog
........\...........\alp_top_dual_Verilog.v
........\...........\Control
........\...........\.......\ipt_clk_rst_top.v
........\...........\.......\ipt_duallink_clk.v
........\...........\.......\ipt_duallink_lmk.v
........\...........\.......\ipt_pll_lut.v
........\...........\.......\ipt_reg.v
........\...........\.......\ipt_rst_ctrl.v
........\...........\.......\ipt_sys_ctrl_decode.v
........\...........\.......\ipt_uwire_ctrl.v
........\...........\.......\ipt_uwire_master.v
........\...........\Datapath
........\...........\........\ipt_3GB_demerge.v
........\...........\........\ipt_duallink_dp.v
........\...........\........\ipt_duallink_dp_rx.v
........\...........\........\ipt_duallink_dp_tx.v
........\...........\........\ipt_duallink_tpg.v
........\...........\........\ipt_retime.v
........\...........\........\ipt_smpte352_insert.v
........\...........\........\TimingGen.v
........\...........\........\Timing_Patterns
........\...........\........\...............\duallink_444_12bit.v
........\...........\........\...............\duallink_444_alpha.v
........\...........\........\...............\ipt_smpte75.v
........\...........\........\...............\rle_75_75_bars.v
........\...........\........\...............\rle_chroma_bars_lut.v
........\...........\........\...............\rle_iq_pluge_lut.v
........\...........\........\...............\timing_pattern.v
........\...........\........\Trs_Crc.v
........\...........\IO
........\...........\..\Descrambler.v
........\...........\..\ipt_crc_chk.v
........\...........\..\ipt_crc_ctrl.v
........\...........\..\ipt_deser_v3.v
........\...........\..\ipt_rx_clkin.v
........\...........\..\ipt_rx_io_top.v
........\...........\..\ipt_rx_top.v
........\...........\..\ipt_rx_vid_mon.v
........\...........\..\ipt_rx_vid_top.v
........\...........\..\ipt_scrambler.v
........\...........\..\ipt_ser.v
........\...........\..\ipt_smpte352_extract.v
........\...........\..\ipt_std_detect.v
........\...........\..\ipt_sync_fifo.v
........\...........\..\ipt_tx_io.v

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