FIFO circuit (first in, first out), internal possession of 16bit × 16word the Dual port RAM, in order to read out has been written into the data. Address because there is no input, so please read and write their own design containing the pointer. By the FIFO circuit output signal of the EF (express the internal data RAM is empty) and the FF signal (that the internal data RAM or above) to express the state of internal RAM and FIFO control of the input signal WEN (Write Enable) and REN ( Reading-enabled). As well as a control in order to better FIFO circuit, AEF (express the internal data RAM is about to air) signal output at the same time.

Packet : 93317434fifo.rar filelist
fifo.vhd

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