Shift register is implemented as a random signal

m\Block2.bdf
.\clock.bdf
.\db\add_sub_6rh.tdf
.\..\add_sub_lsh.tdf
.\..\m.db_info
.\..\m.ipinfo
.\..\m.sim_ori.vwf
.\..\m.sld_design_entry.sci
.\..\prev_cmp_m.asm.qmsg
.\..\prev_cmp_m.fit.qmsg
.\..\prev_cmp_m.map.qmsg
.\..\prev_cmp_m.qmsg
.\..\prev_cmp_m.sim.qmsg
.\..\prev_cmp_m.tan.qmsg
.\..\wed.wsf
.\debounce.bsf
.\debounce.v
.\debounce.v.bak
.\fenpin.bsf
.\fenpin.v
.\fenpin.v.bak
.\fenpinkong.bsf
.\fenpinkong.v
.\fenpinkong.v.bak
.\int_div.bsf
.\int_div.v
.\int_div.v.bak
.\LFSR_8.bsf
.\LFSR_8.v
.\LFSR_8.v.bak
.\m.asm.rpt
.\m.bdf
.\m.done
.\m.dpf
.\m.fit.rpt
.\m.fit.smsg
.\m.fit.summary
.\m.flow.rpt
.\m.map.rpt
.\m.map.summary
.\m.pin
.\m.pof
.\m.qpf
.\m.qsf
.\m.qws
.\m.sim.rpt
.\m.sof
.\m.tan.rpt
.\m.tan.summary
.\m.vwf
.\m_assignment_defaults.qdf
.\Verilog1.v
.\zaoshen.bsf
.\zaoshen.v
.\zaoshen.v.bak
.\db
m

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