On EDA experiment, oneself write the NCO program, can produce more real sine wave, triangular wave and sawtooth wave with VHDL programming, have the modelsim simulation textbench program

FPGA_trainning2013A\verilog_prj\FCW_A.bsf
...................\...........\FCW_A.qip
...................\...........\FCW_A.v
...................\...........\FCW_A_bb.v
...................\...........\NCO.cr.mti
...................\...........\NCO.mpf
...................\...........\NCO_add_ad9767.bsf
...................\...........\NCO_add_ad9767.qip
...................\...........\NCO_add_ad9767.v
...................\...........\NCO_add_ad9767_bb.v
...................\...........\NCO_ALL.bdf
...................\...........\NCO_ALL.v
...................\...........\NCO_Gen.asm.rpt
...................\...........\NCO_Gen.bsf
...................\...........\NCO_Gen.cdf
...................\...........\NCO_Gen.cr.mti
...................\...........\NCO_Gen.done
...................\...........\NCO_Gen.eda.rpt
...................\...........\NCO_Gen.fit.rpt
...................\...........\NCO_Gen.fit.smsg
...................\...........\NCO_Gen.fit.summary
...................\...........\NCO_Gen.flow.rpt
...................\...........\NCO_Gen.hex
...................\...........\NCO_Gen.jdi
...................\...........\NCO_Gen.map.rpt
...................\...........\NCO_Gen.map.summary
...................\...........\NCO_Gen.mpf
...................\...........\NCO_Gen.pin
...................\...........\NCO_Gen.qpf
...................\...........\NCO_Gen.qsf
...................\...........\NCO_Gen.sof
...................\...........\NCO_Gen.sta.rpt
...................\...........\NCO_Gen.sta.summary
...................\...........\NCO_Gen.v
...................\...........\NCO_Gen.v.bak
...................\...........\NCO_Gen.ver
...................\...........\NCO_testbench.v
...................\...........\NCO_testbench.v.bak
...................\...........\PLLA.bsf
...................\...........\PLLA.ppf
...................\...........\PLLA.qip
...................\...........\PLLA.v
...................\...........\PLLA_bb.v
...................\...........\ROM_LUT_A.qip
...................\...........\ROM_LUT_A.v
...................\...........\ROM_LUT_A.vPreview
...................\...........\ROM_LUT_A_bb.v
...................\...........\stp3.stp
...................\...........\vsim.wlf
...................\verilog_prj
FPGA_trainning2013A

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