the CS signal used to distribule CHIP out address by verilog HDL

Ex21_HDL2\DEV2812.ACF
.........\DEV2812.FIT
.........\DEV2812.HIF
.........\DEV2812.INC
.........\DEV2812.JAM
.........\DEV2812.JBC
.........\dev2812.mmf
.........\DEV2812.NDB
.........\DEV2812.PIN
.........\DEV2812.POF
.........\dev2812.rpt
.........\dev2812.scf
.........\DEV2812.SNF
.........\DEV2812.SYM
.........\DEV2812.V
.........\LIB.DLS
.........\transcript
.........\U3718964.DLS
Ex21_HDL2

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